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BF904; BF904R
N-channel dual gate MOS-FETs
Rev. 06 -- 13 November 2007 Product data sheet
IMPORTANT NOTICE
Dear customer, As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors, which will be used in future data sheets together with new contact details. In data sheets where the previous Philips references remain, please use the new links as shown below. http://www.philips.semiconductors.com use http://www.nxp.com http://www.semiconductors.philips.com use http://www.nxp.com (Internet) sales.addresses@www.semiconductors.philips.com use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - (c) Koninklijke Philips Electronics N.V. (year). All rights reserved is replaced with: - (c) NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, NXP Semiconductors
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
FEATURES * Specially designed for use at 5 V supply voltage * Short channel transistor with high transfer admittance to input capacitance ratio * Low noise gain controlled amplifier up to 1 GHz * Superior cross-modulation performance during AGC. APPLICATIONS * VHF and UHF applications with 3 to 7 V supply voltage such as television tuners and professional communications equipment. DESCRIPTION Enhancement type field-effect transistor in a plastic microminiature SOT143B and SOT143R package. The transistor consists of an amplifier MOS-FET with source
BF904; BF904R
and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
PINNING PIN 1 2 3 4 SYMBOL s, b d g2 g1 source drain gate 2 gate 1 DESCRIPTION
handbook, halfpage
d 3
d
handbook, halfpage
4
3
4
g2 g1 1
Top view
g2 g1 2
s,b
Top view
2
MAM124
1
MAM125 - 1
s,b
BF904 marking code: %MC.
BF904R marking code: %MD.
Fig.1 Simplified outline (SOT143B) and symbol.
Fig.2 Simplified outline (SOT143R) and symbol.
QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj yfs Cig1-s Crs F drain current total power dissipation operating junction temperature forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure f = 1 MHz f = 800 MHz PARAMETER drain-source voltage CONDITIONS - - - - 22 - - - MIN. - - - - 25 2.2 25 2 TYP. MAX. 7 30 200 150 30 2.6 35 - UNIT V mA mW C mS pF fF dB
Rev. 06 - 13 November 2007
2 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation BF904 BF904R Tstg Tj Note 1. Device mounted on a printed-circuit board. storage temperature operating junction temperature see Fig.3 Tamb 50 C; note 1 Tamb 40 C; note 1 - - -65 - CONDITIONS - - - - MIN.
BF904; BF904R
MAX. 7 30 10 10 200 200 +150 150 V
UNIT mA mA mA mW mW C C
handbook, halfpage
250
MRA770
P tot (mW) 200
BF904 150 BF904R
100
50
0 0 50 100 150 200 Tamb (o C)
Fig.3 Power derating curves.
Rev. 06 - 13 November 2007
3 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
THERMAL CHARACTERISTICS SYMBOL Rth j-a BF904 BF904R Rth j-s thermal resistance from junction to soldering point BF904 BF904R Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-SS IG2-SS Note 1. RG1 connects gate 1 to VGG = 5 V; see Fig.20. PARAMETER gate 1-source breakdown voltage gate 2-source breakdown voltage forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current CONDITIONS VG2-S = VDS = 0; IG1-S = 10 mA VG1-S = VDS = 0; IG2-S = 10 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VG2-S = 4 V; VDS = 5 V; ID = 20 A VG1-S = VDS = 5 V; ID = 20 A VG2-S = 4 V; VDS = 5 V; RG1 = 120 k; note 1 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 5 V note 2 Ts = 92 C Ts = 78 C PARAMETER thermal resistance from junction to ambient CONDITIONS note 1
BF904; BF904R
VALUE 500 550 290 360
UNIT K/W K/W K/W K/W
MIN. 6 6 0.5 0.5 0.3 0.3 8 - -
MAX. 15 15 1.5 1.5 1 1.2 13 50 50
UNIT V V V V V V mA nA nA
DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VDS = 5 V; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL yfs Cig1-s Cig2-s Cos Crs F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 drain-source capacitance noise figure f = 1 MHz f = 1 MHz f = 1 MHz f = 200 MHz; GS = 2 mS; BS = BSopt f = 800 MHz; GS = GSopt; BS = BSopt CONDITIONS pulsed; Tj = 25 C MIN. 22 - 1 1 - - - TYP. 25 2.2 1.5 1.3 25 1 2 MAX. 30 2.6 2 1.6 35 1.5 2.8 UNIT mS pF pF pF fF dB dB
reverse transfer capacitance f = 1 MHz
Rev. 06 - 13 November 2007
4 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
40 Y fs (mS) 30
MLD268
MRA769
handbook, halfpage gain
0
reduction (dB) 10
20 20
30
10
40
50 0 50 0 50 100 150 o T j ( C) 0 1 2 3 VAGC (V) 4
f = 50 MHz.
Fig.4
Transfer admittance as a function of the junction temperature; typical values.
Fig.5
Typical gain reduction as a function of the AGC voltage.
handbook, halfpage
120
MRA771
MLD270
20 ID (mA) 15 2V V G2 S = 4 V 3V 2.5 V
Vunw (dB V) 110
100
10 1.5 V
90
5 1V
80
0
10
20
30
40 50 gain reduction (dB)
0 0 0.4 0.8 1.2 2.0 1.6 V G1 S (V)
VDS = 5 V; VGG = 5 V; fw = 50 MHz. funw = 60 MHz; Tamb = 25 C; RG1 = 120 k.
Fig.6
Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.20.
VDS = 5 V. Tj = 25 C.
Fig.7 Transfer characteristics; typical values.
Rev. 06 - 13 November 2007
5 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
MLD269
MLD271
handbook, halfpage
20
ID (mA) 16
V G1 S = 1.4 V
handbook, halfpage
150
I G1 1.3 V 1.2 V 1.1 V (A) 100
V G2 S = 4 V 3.5 V
3V
12
2.5 V 50
8
1.0 V 0.9 V 2V
4
0 0 2 4 6 8 10 V DS (V)
0 0 0.5 1.0 1.5 2.0 2.5 V G1 S (V)
VG2-S = 4 V. Tj = 25 C.
VDS = 5 V. Tj = 25 C.
Fig.9 Fig.8 Output characteristics; typical values.
Gate 1 current as a function of gate 1 voltage; typical values.
MLD272
MLD273
handbook, halfpage
40
handbook, halfpage
16
y fs (mS) 30
V G2 S = 4 V 3.5 V 3V
ID (mA) 12
20
2.5 V
8
10
4
2V 0 0 4 8 12 16 20 I D (mA)
0 0 10 20 30 40 50 I G1 (A)
VDS = 5 V. VDS = 5 V. Tj = 25 C. VG2-S = 4 V. Tj = 25 C.
Fig.10 Forward transfer admittance as a function of drain current; typical values.
Fig.11 Drain current as a function of gate 1 current; typical values.
Rev. 06 - 13 November 2007
6 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
MLD275
MLD274
handbook, halfpage
12
handbook, halfpage
20
ID (mA)
ID (mA) 15
R G1 = 47 k
68 k 82 k 100 k 120 k 150 k
8
10 180 k 220 k
4
5
0 0 1 2 3 4 VGG (V)
VDS = 5 V; VG2-S = 4 V. RG1 = 120 k (connected to VGG); Tj = 25 C.
0
5
0
2
4
6 V GG = V DS (V)
8
VG2-S = 4 V. RG1 connected to VGG; Tj = 25 C.
Fig.12 Drain current as a function of gate 1 supply voltage (= VGG); typical values; see Fig.20.
Fig.13 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values; see Fig.20.
MLD276
handbook, halfpage
12
ID (mA) 8
V GG = 5 V 4.5 V 4V 3.5 V 3V
handbook, halfpage
40
MLB945
I G1 (A) 30
V GG = 5 V 4.5 V 4V
20
3.5 V 3V
4 10
0 0 2 4 V G2 S (V) 6
0 0 2 4 V G2 S (V) 6
VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG).
VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG).
Fig.14 Drain current as a function of gate 2 voltage; typical values; see Fig.20.
Fig.15 Gate 1 current as a function of gate 2 voltage; typical values; see Fig.20.
Rev. 06 - 13 November 2007
7 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
10 2 handbook, halfpage y is (mS) 10
MLD277
10 3 y rs (S) 10 2 b is
MLD278
10 3
rs (deg) rs
y rs 10 2
1
10
10
g is 10 1 10
102
f (MHz)
10 3
1 10
1 102 f (MHz) 10 3
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
Fig.16 Input admittance as a function of frequency; typical values.
Fig.17 Reverse transfer admittance and phase as a function of frequency; typical values.
10 2
MLD279
10 2
MLD280
handbook, halfpage
10
y fs (mS)
y fs
fs
(deg)
yos (mS) bos 1
10
fs
10 gos 10 1
1 10
1 102 f (MHz) 10 3
10 2 10
102
f (MHz)
10 3
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C.
Fig.18 Forward transfer admittance and phase as a function of frequency; typical values.
Fig.19 Output admittance as a function of frequency; typical values.
Rev. 06 - 13 November 2007
8 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
VAGC R1 10 k
C1 4.7 nF C3 12 pF
C2 R GEN 50 VI R2 50 4.7 nF
DUT R G1
L1
450 nH
C4 4.7 nF
RL 50
VGG
V DS
MLD171
Fig.20 Cross-modulation test set-up.
Rev. 06 - 13 November 2007
9 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
Table 1 f (MHz) 40 100 200 300 400 500 600 700 800 900 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 Table 2 Scattering parameters: VDS =5 V; VG2-S = 4 V; ID = 10 mA S11 MAGNITUDE (ratio) 0.989 0.985 0.976 0.958 0.942 0.918 0.899 0.876 0.852 0.823 0.800 0.750 0.719 0.682 0.642 0.602 0.547 0.596 0.682 0.771 0.793 ANGLE (deg) -3.4 -8.3 -16.4 -24.1 -32.0 -39.3 -46.0 -52.6 -58.8 -64.9 -70.9 -82.4 -92.7 -102.5 -109.8 -116.5 -124.9 -128.7 -132.6 -142.5 -157.5 S21 MAGNITUDE (ratio) 2.420 2.414 2.368 2.301 2.251 2.170 2.080 2.001 1.924 1.829 1.747 1.621 1.535 1.424 1.349 1.283 1.130 1.018 0.979 0.804 0.541 ANGLE (deg) 175.7 169.1 158.8 148.5 138.8 129.5 120.7 112.1 103.2 94.7 86.5 70.7 54.6 39.4 22.5 1.1 -15.1 -49.1 -79.4 -116.2 -153.5 S12 MAGNITUDE (ratio) 0.000 0.001 0.003 0.004 0.005 0.005 0.005 0.005 0.005 0.005 0.005 0.005 0.008 0.010 0.013 0.018 0.014 0.040 0.077 0.120 0.149 ANGLE (deg) 79.9 78.3 80.3 73.7 70.7 67.2 67.8 68.6 72.9 78.7 88.3 120.5 139.8 137.8 156.8 175.1 172.6 -163.9 -164.0 178.8 158.3
BF904; BF904R
S22 MAGNITUDE (ratio) 0.993 0.992 0.987 0.980 0.974 0.966 0.958 0.951 0.944 0.937 0.933 0.928 0.930 0.924 0.928 0.928 0.887 0.837 0.778 0.629 0.479 ANGLE (deg) -1.6 -3.9 -7.8 -11.4 -15.2 -18.7 -22.2 -25.5 -28.9 -32.1 -35.2 -41.7 -48.4 -54.9 -62.9 -73.1 -81.0 -95.8 -109.6 -119.5 -119.9
Noise data: VDS = 5 V; VG2-S = 4 V; ID = 10 mA f (MHz) 800 Fmin (dB) 2.00 opt (ratio) 0.686 (deg) 49.6 rn 50.40
Rev. 06 - 13 November 2007
10 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
PACKAGE OUTLINES Plastic surface mounted package; 4 leads
BF904; BF904R
SOT143B
D
B
E
A
X
y vMA HE
e bp wM B
4
3
Q
A
A1 c
1
b1 e1
2
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT143B
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
Rev. 06 - 13 November 2007
11 of 14
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904; BF904R
Plastic surface mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y vMA HE
e bp wM B
3
4
Q
A
A1 c
2
b1 e1
1
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT143R
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-03-10
Rev. 06 - 13 November 2007
12 of 14
NXP Semiconductors
BF904; BF904R
N-channel dual gate MOS-FETs
Legal information
Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
Rev. 06 - 13 November 2007
13 of 14
NXP Semiconductors
BF904; BF904R
N-channel dual gate MOS-FETs
Revision history
Revision history Document ID BF904_904R_N_6 Modifications: BF904_904R_5 (9397 750 05898) BF904R_4 (9397 750 02668) BF904R_3 BF904R_2 BF904R_1 Release date 20071113 Data sheet status Product data sheet Product specification Product specification Product specification Change notice Supersedes BF904_904R_5 BF904R_4 BF904R_3 BF904R_2 BF904R_1 -
*
Fig. 1 and 2 on page 2; Figure note changed
19990517 19970905 19950425 -
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2007 Document identifier: BF904_904R_N_6

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